As bulk CMOS devices are scaled to the 22 nm node and beyond, a trade-off is emerging between controlling short channel effects (SCE) and threshold voltage (Vt), and reducing gate induced drain leakage (GIDL). High channel doping and abrupt source/drain profiles are used in CMOS design to suppress the short channel effect. For low stand-by power technologies, channel doping is expected to reach 1019/cm3 at the 22 nm node. However, the combination of high channel doping and abrupt source/drain profiles disadvantageously gives rise to an exponential increase of GIDL current near the drain junction in the off-state. For example, simulation results show that GIDL current will be orders of magnitude higher (˜5 nA/μm) than the off-current target (˜30-300 pA/μm) in low-power technologies.
The threshold voltage (Vt) variation due to random dopant number fluctuation in the device body is another limiting factor for bulk CMOS for the 22 nm node and beyond. Conventional devices use halo or pocket doping to create a heavily doped region in the substrate. This heavily doped region helps with the SCE and Vt control, but disadvantageously increases GIDL because the heavily doped region that is formed by halo or pocket doping overlaps or directly contacts the source and drain regions of the FET. Super-steep retro-grade well (SSRW) structures have been used to address the short channel effect control and Vt variability issues by using an undoped channel layer on top of a heavily doped ground plane with a doping concentration on the order of 1019/cm3. But SSRW structures are not suitable for low-power technologies, due to the high junction leakage current arising from band-to-band tunneling between a heavily doped ground plane and heavily doped source/drain regions.
Conventional halo design with high channel doping and abrupt junctions results in reduced effective tunneling distance near the drain-to-body P/N junction. FIG. 1 shows data plots 110 that depict an exponential relationship between band to band tunneling (BTBT) current and tunneling distance. Based on the trend in FIG. 1, an exponential rise in GIDL current is projected for device scaling from the 45 nm node to the 22 nm node, as shown in FIG. 2.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.